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FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with 2V Undershoot Protection and Selectable Level Shifting
August 2001 Revised October 2006
FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with 2V Undershoot Protection and Selectable Level Shifting
General Description
The Fairchild Universal Bus Switch FSTUD32450 provides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit...40-bit of high-speed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The FSTUD32450 is designed to allow "customer" configuration control of the enable connections. The device can be organized as either a ten 4-bit, eight 5-bit, four 10-bit, two 20-bit or one 40-bit enabled bus switch. Also achievable are 8-bit and 16-bit enabled configurations (see Functional Description). The device's bit configuration is controlled through select pin logic. (see Truth Table). When OEx is LOW, Port Ax is connected to Port Bx. When OEx is HIGH, the switch is OPEN. The A and B Ports are protected against undershoot to support an extended range to 2.0V below ground. Fairchild's integrated Undershoot Hardened Circuit (UHC(R)) senses undershoot at the I/O, and responds by preventing voltage differentials from developing and turning the switch on. Another innovative device feature is the addition of a level shifting select pin, "S2 and S5". When S2 and S5 are LOW, the device behaves as a standard N-MOS switch. When S2 and S5 are HIGH, a diode to VCC is integrated into the circuit allowing for level shifting between 5V inputs and 3.3V outputs.
Features
s Undershoot protected to 2V (A and B Ports) s Voltage level shifting s 4: switch connection between two ports s Minimal propagation delay through the switch s Low lCC s Zero bounce in flow-through mode s Control inputs compatible with TTL level s See Applications Notes AN-5008 and AN-5021 for UHC details s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Applications Note
Select pins S0, S1, S2, S3, S4 and S5 are intended to be used as static user configurable control pins. The AC performance of these pins has not been characterized or tested. Switching of these select pins during system operation may temporarily disrupt output logic states and/or enable pin controls. 40-bit configuration can be achieved by connecting the OE1 and the OE6 pins to together.
Ordering Code:
Order Number FSTUD32450G (Note 1)(Note 2) Package Number BGA114A Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering code "G" indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
UHC(R) is a registered trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS500447
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FSTUD32450
Connection Diagram
Pin Assignment for FBGA
Pin Descriptions
Pin Name OE1, OE2, OE3, OE4, OE5, OE6, OE7, OE8 OE9, OE10 1A, 2A, 3A, 4A 1B, 2B, 3B, 4B S0, S1, S3, S4 S2, S5 Bus A Bus B Bit Configuration Enables Level Shifting Diode Enables Description Bus Switch Enables
FBGA Pin Assignments
1 A B C D E F G H J (Top Thru View) K L M N P R T U V W 1A4 1A6 1A8 1A10 2A2 2A4 2A6 2A8 2A10 OE4 3A10 3A8 3A6 3A4 3A2 4A10 4A8 4A6 4A4 2 1A2 1A5 1A7 1A9 2A1 2A3 2A5 2A7 2A9 OE8 3A9 3A7 3A5 3A3 3A1 4A9 4A7 4A5 4A2 3 OE1 1A1 1A3 GND S0 S1 VCC GND GND GND GND GND GND S5 VCC OE10 4A3 4A1 OE7 4 OE2 1B1 1B3 OE5 VCC S2 GND GND GND GND GND GND VCC S4 S3 GND 4B3 4B1 OE6 5 1B2 1B5 1B7 1B9 2B1 2B3 2B5 2B7 2B9 OE9 3B9 3B7 3B5 3B3 3B1 4B9 4B7 4B5 4B2 6 1B4 1B6 1B8 1B10 2B2 2B4 2B6 2B8 2B10 OE3 3B10 3B8 3B6 3B4 3B2 4B10 4B8 4B6 4B4
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FSTUD32450
Logic Diagrams
20-Bit Configuration
10-Bit Configuration
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FSTUD32450
5-Bit Configuration
4-Bit Configuration
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FSTUD32450
Functional Description
The device can also be configured as an 8 and 16-bit device by grounding the unused pins in Configurations 2 and 1 respectively. The 8-bit configuration may also be achieved by tying two of the 4-bit enables from configuration together and tying the remaining enable pin (OE) HIGH.
Truth Tables
(X
VCC or GND) Select Pin
(see Functional Description) S2, S5 L H Mode Std. NMOS Switch Level Shifting Diode Enabled
20-Bit Configuration (S0 OE1 L H OE2 X X
S1
L) Inputs/Outputs 1A1-10 1B1-10, 2A1-10 Z 2B1-10
Inputs OE3 X X S3 Inputs Inputs/Outputs OE6 L H OE7 X X OE8 X X OE9 X X OE10 X X 3A1-10 3B1-10, 4A1-10 Z 4B1-10 OE4 X X S4 L OE5 X X
10-Bit Configuration (S0 OE1 L L H H OE2 X X X X
L, S1 Inputs OE3 X X X X
H) Inputs/Outputs OE4 L H L H S3 L, S4 OE9 L H L H H Inputs/Outputs OE10 X X X X 4A1-10 4AX 4AX Z Z 4B1-10 4BX 4BX 3AX Z 3A1-10 3AX Z 3BX 3B1-10 3BX OE5 X X X X 1A1-10 1AX 1AX Z Z 1B1-10 1BX 1BX 2AX Z 2A1-10 2AX Z 2BX 2B1-10 2BX
Inputs OE6 L L H H OE7 X X X X OE8 X X X X
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FSTUD32450
Truth Tables
(Continued) H, S1 OE4 L H L H L H L H L H L H L H L H S3 Inputs H, S4 L) Inputs/Outputs OE5 X X X X X X X X X X X X X X X X L Inputs/Outputs OE9 L H L H L H L H L H L H L H L H OE10 X X X X X X X X X X X X X X X X 4A1-5, 4B1-5 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax Z Z Z Z Z Z Z Z 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Ay 4Ay 4Ay 4Ay Z Z Z Z 4A6-10, 4B6-10 4Ay 4Ay 4Ay 4Ay Z Z Z Z 4By 4By 4By 4By 3Ax 3Ax Z Z 3Ax 3Ax Z Z 3Bx 3Bx 3Ay Z 3Ay Z 3By 4By 4By 4By 4By 3Ax 3Ax Z Z 3Bx 3Bx 3Ay Z 3By 3Ay Z 3By 3A1-5, 3B1-5 3Ax 3Ax Z Z 3Bx 3Bx 3Ay Z 3By 3Ay Z 3By 3Bx 3Bx 3Ay Z 3By 3A6-10, 3B6-10 3Ay Z 3By 3By 1A1-5, 1B1-5 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax Z Z Z Z Z Z Z Z 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Ay 1Ay 1Ay 1Ay Z Z Z Z 1A6-10, 1B6-10 1Ay 1Ay 1Ay 1Ay Z Z Z Z 1By 1By 1By 1By 2Ax 2Ax Z Z 2Ax 2Ax Z Z 2Bx 2Bx 2Ay Z 2Ay Z 2By 1By 1By 1By 1By 2Ax 2Ax Z Z 2Bx 2Bx 2Ay Z 2By 2Ay Z 2By 2A1-5, 2B1-5 2Ax 2Ax Z Z 2Bx 2Bx 2Ay Z 2By 2Ay Z 2By 2Bx 2Bx 2Ay Z 2By 2A6-10, 2B6-10 2Ay Z 2By 2By
5-Bit Configuration (S0 Inputs OE1 L L L L L L L L H H H H H H H H OE2 L L L L H H H H L L L L H H H H OE3 L L H H L L H H L L H H L L H H
OE6 L L L L L L L L H H H H H H H H
OE7 L L L L H H H H L L L L H H H H
OE8 L L H H L L H H L L H H L L H H
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FSTUD32450
Truth Tables
(Continued) S1 H) Inputs/Outputs OE4 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H OE5 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H 1A1-4, 1B1-4 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax 1Ax Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Bx 1Ay 1Ay 1Ay 1Ay 1Ay 1Ay 1Ay 1Ay Z Z Z Z Z Z Z Z 1A5-8, 1B5-8 1Ay 1Ay 1Ay 1Ay 1Ay 1Ay 1Ay 1Ay Z Z Z Z Z Z Z Z 1By 1By 1By 1By 1By 1By 1By 1By 2Ax 2Ax 2Ax 2Ax Z Z Z Z 2Ax 2Ax 2Ax 2Ax Z Z Z Z 2Bx 2Bx 2Bx 2Bx 2Ay 2Ay Z Z 2Ay 2Ay Z Z 2By 2By 1Az 2Az Z 1Az 2Az Z 1Bz 2Bz 1By 1By 1By 1By 1By 1By 1By 1By 2Ax 2Ax 2Ax 2Ax Z Z Z Z 2Bx 2Bx 2Bx 2Bx 2Ay 2Ay Z Z 2By 2By 1Az 2Az Z 1Bz 2Bz 1Az 2Az Z 1Bz 2Bz 2Ay 2Ay Z Z 2By 2By 1Az 2Az Z 1Bz 2Bz 1Az 2Az Z 1Bz 2Bz 2A3-6, 2B3-6 2Ax 2Ax 2Ax 2Ax Z Z Z Z 2Bx 2Bx 2Bx 2Bx 2Ay 2Ay Z Z 2By 2By 1Az 2Az Z 1Bz 2Bz 1Az 2Az Z 1Bz 2Bz 2Ay 2Ay Z Z 2By 2By 1Az 2Az Z 1Bz 2Bz 1Az 2Az Z 1Bz 2Bz 2Bx 2Bx 2Bx 2Bx 2Ay 2Ay Z Z 2By 2By 1Az 2Az Z 1Bz 2Bz 1Az 2Az Z 1Bz 2Bz 2A7-10, 2B7-10 2Ay 2Ay Z Z 2By 2By 1Az 2Az Z 1Bz 2Bz 1Az 2Az Z 1Bz 2Bz 2By 2By 1Az 2Az Z 1Bz 2Bz 1A9-10, 2B9-10 2A1-2, 2B1-2 1Az 2Az Z 1Bz 2Bz 1Bz 2Bz
4-Bit Configuration (S0 Inputs OE1 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H OE2 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H OE3 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H
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FSTUD32450
Truth Tables
(Continued)
4-Bit Configuration (continued) S3 Inputs OE6 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H OE7 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H OE8 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H OE9 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H OE10 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H 4A1-4, 4B1-4 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax 4Ax Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Bx 4Ay 4Ay 4Ay 4Ay 4Ay 4Ay 4Ay 4Ay Z Z Z Z Z Z Z Z 4A5-8, 4B5-8 4Ay 4Ay 4Ay 4Ay 4Ay 4Ay 4Ay 4Ay Z Z Z Z Z Z Z Z 4By 4By 4By 4By 4By 4By 4By 4By 3Ax 3Ax 3Ax 3Ax Z Z Z Z 3Ax 3Ax 3Ax 3Ax Z Z Z Z 3Bx 3Bx 3Bx 3Bx 3Ay 3Ay Z Z 3Ay 3Ay Z Z 3By 3By 3Az 4Az Z 3Az 4Az Z 3Bz 4Bz 4By 4By 4By 4By 4By 4By 4By 4By 3Ax 3Ax 3Ax 3Ax Z Z Z Z 3Bx 3Bx 3Bx 3Bx 3Ay 3Ay Z Z 3By 3By 3Az 4Az Z 3Bz 4Bz 3Az 4Az Z 3Bz 4Bz 3Ay 3Ay Z Z 3By 3By 3Az 4Az Z 3Bz 4Bz 3Az 4Az Z 3Bz 4Bz S4 H Inputs/Outputs 3A3-6, 3B3-6 3Ax 3Ax 3Ax 3Ax Z Z Z Z 3Bx 3Bx 3Bx 3Bx 3Ay 3Ay Z Z 3By 3By 3Az 4Az Z 3Bz 4Bz 3Az 4Az Z 3Bz 4Bz 3Ay 3Ay Z Z 3By 3By 3Az 4Az Z 3Bz 4Bz 3Az 4Az Z 3Bz 4Bz 3Bx 3Bx 3Bx 3Bx 3Ay 3Ay Z Z 3By 3By 3Az 4Az Z 3Bz 4Bz 3Az 4Az Z 3Bz 4Bz 3A7-10, 3B7-10 3Ay 3Ay Z Z 3By 3By 3Az 4Az Z 3Bz 4Bz 3Az 4Az Z 3Bz 4Bz 3By 3By 3Az 4Az Z 3Bz 4Bz 3A1-2, 3B1-2 4A9-10, 3B9-10 3Az 4Az Z 3Bz 4Bz 3Bz 4Bz
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FSTUD32450
Absolute Maximum Ratings(Note 3)
Supply Voltage (VCC) DC Switch Voltage (VS) (Note 4) DC Input Control Pin Voltage (VIN) (Note 5) DC Input Diode Current (lIK) VIN 0V DC Output (IOUT) Current DC VCC/GND Current (ICC/IGND) Storage Temperature Range (TSTG)
0.5V to 7.0V 2.0V to 7.0V 0.5V to 7.0V 50 mA
128 mA
Recommended Operating Conditions (Note 6)
Power Supply Operating (VCC) Input Voltage (VIN) Output Voltage (VOUT) Free Air Operating Temperature (TA) 4.0V to 5.5V 0V to 5.5V 0V to 5.5V -40 qC to 85 qC
/ 100 mA 65qC to 150 qC
Note 3: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 4: VS is the voltage observed/applied at either the A or B Ports across the switch. Note 5: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Note 6: Unused control inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC Symbol VIK VIH VIL VOH II IOZ RON Parameter Clamp Diode Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage Input Leakage Current OFF-STATE Leakage Current Switch On Resistance (Note 8) (V) 4.5 4.0-5.5 4.0-5.5 4.5-5.5 5.5 0 5.5 4.5 4.5 4.5 4.0 4.5 ICC Quiescent Supply Current 5.5 4 4 8 11 35 See Figure 4 2.0 0.8 TA Min
40 qC to 85 qC
Typ (Note 7) Max Units V V V V IIN Conditions
1.2
18 mA
HIGH 4.5V d VCC d 5.5V HIGH 4.5V d VCC d 5.5V VCC
IF S2 IF S2 S2 VIN VIN VIN VIN VIN VIN S2 S2 S2 S5
r1.0
10
PA PA PA : : : : : PA PA
mA mA mA V
0 d VIN d 5.5V 5.5V 0V, IIN 0V, IIN 2.4V, IIN 2.4V, IIN 2.4V, IIN S5 S5 S5 64 mA, S2 30 mA, S2 15 mA, S2 15 mA, S2 15 mA, S2 S5 S5 S5 S5 S5 0V or VCC 0V or VCC 0V 0V VCC 0 0 0 0 d A, B d VCC
r1.0
7 7 12 20 50 3 10 1.5
GND, VIN VCC, OEx VCC, OEx
VCC or GND, IOUT VCC, VIN GND, VIN
VCC or GND, IOUT VCC or GND, IOUT 0V VCC
ICCT
Increase in ICC per Control Input 5.5
2.5 4.0
One Control Input at 3.4V Other Inputs at VCC or GND, S2 One Control Input at 3.4V Other Inputs at VCC or GND, S2 0.0 mA t IIN t 50 mA OEx 5.5V
VIKU
Voltage Undershoot
5.5
5.0V and TA
2.0
Note 7: Typical values are at VCC
25qC
Note 8: Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B) pins.
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FSTUD32450
AC Electrical Characteristics
TA Symbol Parameter VCC Min tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ Propagation Delay Bus-to-Bus (Note 9) Output Enable Time Output Disable Time Sel (S0, 1) to Output Enable Time Sel (S0, 1) to Output Disable Time 1.5 1.5 1.5 1.5 CL
40 qC to 85 qC,
RD 500: 4.0V Max 0.25 7.0 7.2 7.5 7.7 ns ns ns ns ns VI VI VI 6.7 7.0 7.5 VI VI VI VI VI VI OPEN 7V for tPZL OPEN for tPZH 7V for tPLZ OPEN for tPHZ 7V for tPZL OPEN for tPZH 7V for tPLZ OPEN for tPHZ Figures 2, 3 Figures 2, 3 Figures 2, 3 Figures 2, 3 Figures 2, 3 Units Conditions (S2 S5 0V) Figure Number VCC Min
50pF, RU
4.5 - 5.5V Max 0.25 6.5
Note 9: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
AC Electrical Characteristics: Translating Diode
TA Symbol Parameter CL
40 qC to 85 qC,
RD 500: VCC 4.5 - 5.5V Max 0.25 ns ns ns ns ns VI VI VI VI VI VI VI VI VI OPEN 7V for tPZL OPEN for tPZH 7V for tPLZ OPEN for tPHZ 7V for tPZL OPEN for tPZH 7V for tPLZ OPEN for tPHZ Figures 2, 3 Figures 2, 3 Figures 2, 3 Figures 2, 3 Figures 2, 3 Units Conditions (S2 S5 VCC) Figure Number
50pF, RU
Min tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ Propagation Delay Bus-to-Bus (Note 10) Output Enable Time Output Disable Time Sel (S0, 1) to Output Enable Time Sel (S0, 1) to Output Disable Time 1.5 1.5 1.5 1.5
10.0 9.0 11.0 10.0
Note 10: This parameter is guaranteed by design but is not tested. This bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
Symbol CIN CI/O
Note 11: TA
(Note 11)
Parameter Typ 4 8 Max Units pF pF VCC Conditions 5.0V, VIN 0V 0V
Control Pin Input Capacitance Input/Output Capacitance "OFF State"
25qC, f
VCC, OE
5.0V, VIN
1 MHz, Capacitance is characterized but not tested.
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FSTUD32450
Undershoot Characteristic (Note 12)
Symbol VOUTU Parameter Output Voltage During Undershoot Min 2.5 TBD Typ VOH 0.3 TBD Max Units V V S2 S2 S5 S5 Conditions 0V, Figure 1 VCC
Note 12: This test is intended to characterize the device's protective capabilities by maintaining output signal integrity during an input transient voltage undershoot event.
FIGURE 1.
Device Test Conditions
Parameter VIN R1 R2 VTRI VCC Value see Waveform 100K 11.0 5.5 Units V
Transient Input Voltage (VIN) Waveform
:
V V
AC Loading and Waveforms
Note: Input driven by 50: source terminated in 50: Note: CL includes load and stray capacitance Note: Input Frequency 1.0 MHz, tW 500 ns
FIGURE 2. AC Test Circuit
FIGURE 3. AC Waveforms
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FSTUD32450
FIGURE 4.
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FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with 2V Undershoot Protection and Selectable Level Shifting
Physical Dimensions inches (millimeters) unless otherwise noted
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A
Technology Description
The Fairchild Switch family derives from and embodies Fairchild's proven switch technology used for several years in its 74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 13 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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